An important consideration in integrated circuit (IC) design is conserving power in the manufactured IC. Accordingly, EDA tools support power conservation in IC design. Traditionally, the EDA design flow and associated EDA tools have focused on either analog design or digital design. Consequently, EDA tools for mixed-signal designs with both analog and digital design blocks have treated mixed-signal designs as an analog design supplemented with a digital black box, or a digital design supplemented with an analog black box. Treating the analog design block or digital design block as a black box ignores interaction between the analog and digital designs, such as multiple feedback loops and other complex interactions. One such interaction relates to the implementation of low power design with mixed-signal designs. An oversimplified verification of the mixed-signal IC design may fail to ensure that the manufactured mixed-signal IC design meets the low power design requirements when the IC design is taped out and ultimately fabricated.
In one approach, to more accurately perform verification on a mixed-signal IC design, a transient simulation simulates the time-varying behavior of the mixed-signal IC design circuit in the time domain. States or values are measured in the target design, and alerts are triggered by assertions in assertion-based verification to indicate a success or a failure of the mixed-signal IC design to meet a low power design requirement. In this approach, the transient simulation is time-consuming and may not be able to exhaust all possible input-output combinations. Also, in this approach, the circuit designer carries the burden of creating an assertion to verify each low power design requirement.
In another approach, to more accurately perform verification on a mixed-signal IC design, a formal verification tool determines whether the mixed-signal IC design meets low power design requirements. Because the formal verification tool is designed for performing verification on digital circuit designs, any analog circuit design blocks are converted in order be compatible with the formal verification tool. This conversion process not only places a burden on the circuit designer, but it also has multiple points of introducing error into the formal verification.